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Display Driver Registry Settings

 

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Registry Locations

The Display Driver Settings are located in registry file under the key name mentioned below. You can use the Colibri Tweak Tool, I.MX6 Display Tool or Vybrid Display to adjust most of these settings.

Colibri Module Windows CE Image Version Registry Location
Colibri PXAxxx before V3.0 [HKLM\Drivers\Display\PXA27x\Config]
Colibri PXAxxx V3.0 and newer [HKLM\Drivers\Display\Colibri]
Colibri VFxx (all) [HKLM\Drivers\Display\Colibri]
Colibri Txx (all) [HKLM\Software\Nvidia Corporation\NVDDI\LCD]
Colibri iMX6 (all) [HKLM\Drivers\Display\Colibri]
Apalis T30 (all) [HKLM\Software\Nvidia Corporation\NVDDI\LCD]
Apalis iMX6 (all) [HKLM\Drivers\Display\Apalis]



Registry Settings

Tegra GPIOs

Whenever a GPIO for the Tegra based modules is used, a special conversion from GPIO name to GPIO number needs to be used:
GPIO A0 → 0, ... GPIO A7 → 7
GPIO B0 → 8, ... GPIO B7 → 15
GPIO C0 → 16, ... GPIO C7 → 23
...

Settings for all Colibri and Apalis Modules

The table below lists all available registry settings for the display driver.

For the Tegra modules, timings only affect the LCD output. For the other outputs, EDID data is read from the screen, and the most appropriate VESA timings are used.

Registry Key Description Valid Settings Default Value Note
CxScreen Horizontal Screen Resolution PXA: 1-1024
Tegra: 1-2048
VFxx: 16-1024
iMX6: 16-4096
640
CyScreen Vertical Screen Resolution PXA: 1-1024
Tegra: 1-2048
VFxx: 4-768
iMX6: 16-2048
480
Bpp Frame Buffer Color Depth 8, 16, 24, 32
VFxx,iMX6: 16, 32
Txx: use MainPanelBpp
8
VFxx: 32
(q)
LDDS Number of LCD Data Lines used 4, 8, 16, 18, 24
VFxx: 15,16,18,24
iMX6: 16,18,24
PCLK Pixel clock in Hz PXA: 203'000 - 52'000'000
Tegra: 203'000-168'000'000
VFxx:203'000 - 60'000'000
iMX6: 203'000 - 170'000'000(u)
25'000'000
PCP Pixel Clock Polarity 0: Data valid on Rising Edge
1: Data valid on Falling Edge
1
OEP Output Enable Polarity(v) 1: ActiveLow
0: ActiveHigh
0
HSW Horizontal Sync Width in Pixels PXA: 1-64
Tegra: 0-8191
i.MX6: 0-1024
2
BLW Begin of Line Width (Back Porch) in Pixels PXA: 1-256
Tegra: -4096-4095
VFxx: 1-256
iMX6: 0-1024
160
ELW End of Line Width (Front Porch) in Pixels PXA: 1-256
Tegra: 0-8191
VFxx: 1-256
iMX6: 0-1024
2
HSP Horizontal Sync Polarity 0: Active High
1: Active Low
0
VSW Vertical Sync Width in Lines PXA: 1-64
Tegra: 0-8191
VFxx, iMX6: 1-256
45
iMX6: 2
BFW Begin of Frame Width (Back Porch) in Lines PXA: 0-255
Tegra: -4096-4095
VFxx: 1-256
iMX6: 0-1024
0
EFW End of Frame Width (Front Porch) in Lines PXA: 0-255
Tegra: 0-8191
VFxx: 1-256
iMX6: 0-1024
0
VSP Vertical Sync Polarity 0: Active High
1: Active Low
0
BL_GPIO GPIO used to Turn On/Off Backlight Any free GPIO, or -1 for None (SODIMM 71) (i)
BL_POL Polarity for Backlight GPIO 0: ActiveLow
1: ActiveHigh
1
DISP_GPIO GPIO used to Turn On/Off Display Power Any free GPIO, or -1 for None (SODIMM 71) (i)
DISP_POL Polarity for Display Power GPIO 0: Active Low
1: Active High
1
DispOnDelay Display Enable (DISP_GPIO) on delay in ms compared to the LCD data signals VFxx,iMX6 : not supported 0 (b)
LCDBS Display signal buffer strength. This value could be changed to reduce EMC problems. PXA270: 0-15
PXA3xx: 0-7
VFxx 0-7
Txx: See Note (p)
iMX6: 0-7
PXA, iMX6 and VFxx: 5
Txx: 0xF1612030
(p)



Settings for Colibri PXAxxx Modules Only

Registry Key Description Valid Settings Default Value Note
Verbosity Bitmask to show additional display driver infos on the debug port. 1: Errors
2: Warnings
4: Initialize
8: Allocation
0 (g)
Type Display Type 0: Passive
1: Active
-1: LCD unit disabled
1
Color color or Monochrome Selection 0: Monochrome
1: Color
1
Dual Dual or Single Panel Selection 0: Single
1: Dual
0
PCLKStall Stops the Pixel Clock if a LCD underrun occurs. This can help if your display is connected over TTL 0 (d)
VideoRAMSize overrides the default value for the video ram. (In bytes) (h)
UseSRAM Reserved internal SRAM for display driver. 0: SRAM not used for display driver
1: maximum available SRAM is used
>1: reserved size in bytes
0 (c)(g)
Blit Blit Hardware Support 0: use emulation
1: XScale optimized
2: use 2D acceleration if possible
2
Cursor Mouse Cursor Mode 2: Hardware cursor
1: Software Cursor
0: hide the mouse cursor
2
EdidSlaveAddr 7-bit i2c address where the EDID EEPROM containing display timing information is located. 0x00-0x7f (e) (f)
DispOffDelay Display Enable (DISP_GPIO) off delay in ms compared to the LCD data signals 0 (b)



Settings for Colibri Txx and Apalis Txx Modules Only

The following registry entries are located at:
[HKLM\Software\Nvidia Corporation\NVDDI]

Registry Key Description Valid Settings Default Value Note
Enable2D Enable hardware 2D acceleration in display driver 0: Off
1: On
1
HwCursor Mouse Cursor 1: Hardware cursor
0: Software Cursor
1
MainPanelBpp Frame Buffer Color Depth 16, 32 16
DesktopWidth Framebuffer Width 1-2048 640 (j)
DesktopHeight Framebuffer Height 1-2048 480 (j)
DesktopScaleMode Behavior if Desktop does not match Screen 1: Scale, preserve aspect ratio
2: Center the desktop
3: Scale
1
HDMIHotplugBehavior Behavior of the HotPlug pin 1: Connect HDMI on HotPlug interrupt
2: Do not connect HDMI, but update list of available display modes
1
BootupStyle Active Display at startup (bit mask) Active Display
- 0x00001: LCD
- 0x00006: TvOut (NTSC)
- 0x0000a: TvOut (PAL)
- 0x00010: HDMI
- 0x00020: CRT
Additional Flags
- 0x20000: Cinema Mode
- 0x30000: Cinema and Mirror Mode
Colibri: LCD
Apalis: LCD and CRT
since 1.3beta3
(k)(m)
HotPlugStyle Active Display while HotPlug pin is active (bit mask) Active Display
- 0x00001: LCD
- 0x00006: TvOut (NTSC)
- 0x0000a: TvOut (PAL)
- 0x00010: HDMI
- 0x00020: CRT
Additional Flags
- 0x20000: Cinema Mode
- 0x30000: Cinema and Mirror Mode
Colibri: LCD and HDMI
Apalis: CRT and HDMI
since 1.3
(k)(m)
FilterScaledDesktops Filter, if display resolution is not equal to desktop resolution 0: do not filter
1: activate filter
0
ColorSize Native display color depth 1: 111
2: 222
3: 333
4: 444
5: 555
6: 565
7: 666
8: 332
9: 888
7 (n)

The following registry entries are located at:
[HKLM\Software\Nvidia Corporation\NVDDI\LCD]

Registry Key Description Valid Settings Default Value Note
forcePLLD Force the PLLD to be used as source clk. Use this if you need a more accurate pixel clock. Otherwise the best fitting clock source is chosen by the driver. 0: set by driver
1: force PLLD
0 since 1.4beta1
LvdsEnable Enable or disable LVDS converter 0: Disabled
1: Enabled
0 since 2.0beta3, Apalis T30 only.
LvdsMode Single or dual channel LVDS mode 0: Dual channel
1: Single channel
0 since 2.0beta3, Apalis T30 only.
LvdsBitMode 18 bit (6 bit per colour) or 24 bit (8 bit per colour) mode 0: 24 bit
1: 18 bit
0 since 2.0beta3, Apalis T30 only.
LvdsMap 24 bit / 18 bit compatible (JEIDA) or Common 24 bit colour mode (VESA) 0: VESA
1: JEIDA
0 since 2.0beta3, Apalis T30 only.
LvdsRS LVDS swing mode: standard LVDS value or reduced swing reduces EMI and power consumption, suitable for short cables 0: reduced
1: standard
0 since 2.0beta3, Apalis T30 only.

Settings for Colibri VFxx Modules Only

Registry Key Description Valid Settings Default Value Note
UseSplashSettings Ignores additional registry parameters and uses the configuration used for the splash screen. 0/1 1
VideoRamSize Configures the amount of bytes used for display frame buffer, overlays and back buffers 0-32MB 0x800000-0xC00000
(8-12MB depending on the display resolution)
(r)
ActivateDisplayEvent If present, this key forces the display to show splash screen until the specified named OS event is set. SYSTEM/ShellAPIReady (s)
FirstRefreshDelay Delay (in milliseconds) between the driver loading and display initialization,
this may prevent "black screen" between splash screen and desktop/application
0-n 10000 (t)

Settings for i.MX6 Modules Only

Registry Key Description Valid Settings Default Value Note
Out Output port, is valid only on Apalis, on Colibri only 0 is supported.
0 - VGA/Colibri
1 - Parallel LCD
2 - LVDS Channel 0
3 - LVDS Channel 1
4 - LVDS dual channel
0/4 0
VideoMemSize Configures the amount of bytes used for video memory 0-128MB 0x800000-0x2000000
(8MB on Colibri-32MB on Apalis)

Notes:
(a) Default value depends on Type/Color/Dual settings
(b) In PXA Images later than V3.3 negative values allowed. Negative values are not supported in the Bootloader.
     In Tegra Images supported since V1.3, no negative values allowed.
(c) PXA320 only
(d) Available in Image V3.6 beta 1 and later
(e) Any value outside this range disables the EDID feature
(f) Available in Image V3.7beta1 and later
(g) Available in Image V3.4beta2 and later
(h) For more information about using VideoRAMSize (overriding the video RAM size) see VideoRAM.
(i) If BL_GPIO and DISP_GPIO are set to the same value, the Display Driver stops the LCD controller when turning off the backlight
The default values for BL_GPIO and DISP_GPIO depend on the Colibri module; the default is the GPIO which is routed to SODIMM 71.
(j) To avoid stretching, we recommend to set the framebuffer resolution identical to the screen resolution
(k) Do a logical OR of 1 or 2 displays. For dual display, optionally add the cinema or mirror bits. The default is mirror mode, i.e. both screen show the same content. In cinema mode, videos are shown on the 2nd display.
For example 0x20011: LCD and HDMI (Cinema) - The desktop is shown on the LCD output, videos are shown on the HDMI output.
(m) Not all combinations are tested.
(n) This parameter is located in [HKLM\Software\Nvidia Corporation\NVDDI\LCD]. The display controller uses dithering to emulate the color depth given in the Bpp parameter.
(p) For Txx modules enter the register value of the LCDCFG2 pad control register. More information about this setting can be found in the Technical Reference Manual - Tegra2, Tegra3. To minimize the drive strength try to set lcdbs to 0xF0000000.
(q) Currently maximum display resolution supported on Vybrid VF50 is 1024x768@16BPP (XGA), 32BPP not possible at this resolution.
(r) This parameter is considered only if the "UseSplashSettings" parameter is set to 0. The default value is 4 or 8MB, depending on resolution and bit depth.
(s) See Splash Screen for a usage sample
(t) If the ActivateDisplayEvent is used, this value is the timeout used to wait on the event.
(u) Actual maximum value may vary depending on memory bandwidth and other factors, please check the processor reference manual for more detailed specifications.
(v) Output Enable polarity can't be changed on Vybrid, it's always positive.

Display Timings

The following picture shows the naming convention for display timings in the registry settings.

Front: Beginning of line/frame and is also known as Back Porch in many display datasheets.
Back: End of line/frame and is also known as Front Porch in many display datasheets.