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DMA Library API

 

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Library for DMA handling, including channel allocation and DMA transfer control.

Data Structures

struct  DMA_GLOBALSMemory mapped DMA Globals structure - sorted by DMA channel. More...

Macros

#define  DMA_VER_MAJ  1
#define  DMA_VER_MIN  3
#define  DMA_VER_BUILD  1
#define  DMA_MAX_CHAN  32
number of available DMA channels More...
#define  DMA_USAGE_LEN  32
maximum string length for a descriptive text (DMA channel usage) More...
#define  DMA_SHARED_FILENAME  (TEXT("ColibriDmaGlobals"))
Memory mapped filename used by the DMALib for interprocess sharing of DMA data structures. More...
#define  PERIPH_SSP1RX  (13)
#define  PERIPH_SSP1TX  (14)
#define  PERIPH_SSP2RX  (15)
#define  PERIPH_SSP2TX  (16)
#define  PERIPH_SSP3RX  (66)
#define  PERIPH_SSP3TX  (67)
#define  PERIPH_SSP4RX  (71)
#define  PERIPH_SSP4TX  (72)
#define  PERIPH_CIF1  (68)
#define  PERIPH_CIF2  (69)
#define  PERIPH_CIF3  (70)
#define  DCMD_INCSRCADDR  (1 << 31)
Source Address Increment. More...
#define  DCMD_INCTRGADDR  (1 << 30)
Target Address Increment. More...
#define  DCMD_FLOWSRC  (1 << 29)
Source Flow Control. More...
#define  DCMD_FLOWTRG  (1 << 28)
Target Flow Control. More...
#define  DCMD_CIF_DMA  (1 << 27)
Create a PXA3xx CIF descriptor. More...
#define  DCMD_CMPEN  (1 << 25)
Descriptor Compare Enable. More...
#define  DCMD_ADDRMODE  (1 << 23)
Addressing Mode. More...
#define  DCMD_STARTIRQEN  (1 << 22)
Start Interrupt Enable. More...
#define  DCMD_ENDIRQEN  (1 << 21)
End Interrupt Enable. More...
#define  DCMD_FLYBYS  (1 << 20)
Fly-By Source (PXA270 only) More...
#define  DCMD_FLYBYT  (1 << 19)
Fly-By Target (PXA270 only) More...
#define  DCMD_BSIZE8  (1 << 16)
#define  DCMD_BSIZE16  (2 << 16)
#define  DCMD_BSIZE32  (3 << 16)
#define  DCMD_BWIDTH8  (1 << 14)
#define  DCMD_BWIDTH16  (2 << 14)
#define  DCMD_BWIDTH32  (3 << 14)
#define  DCMD_LENGTH  0x01fff
Length of Transfer in Bytes (MASK) More...
#define  DCSR_RUN  (1 << 31)
Run Bit (read / write) More...
#define  DCSR_NODESC  (1 << 30)
No-Descriptor Fetch (read / write) More...
#define  DCSR_STOPIRQEN  (1 << 29)
Stop Interrupt Enable (when the descriptor is done) (read / write) More...
#define  DCSR_EORIRQEN  (1 << 28)
End-of-Receive Interrupt Enable. More...
#define  DCSR_EORJMPENT  (1 << 27)
Jump to next Descriptor on End-of-Receive. More...
#define  DCSR_EORSTOPEN  (1 << 26)
Stop Channel on End-of-Receive. More...
#define  DCSR_SETCMPST  (1 << 25)
Set Descriptor Compare Status. More...
#define  DCSR_CLRCMPST  (1 << 24)
Clear Descriptor Compare Status. More...
#define  DCSR_CMPST  (1 << 10)
Descriptor Compare Status. More...
#define  DCSR_EORINT  (1 << 9)
End of Receive. More...
#define  DCSR_REQPEND  (1 << 8)
Request Pending (read-only) More...
#define  DCSR_RASINTR  (1 << 4)
Request after Channel Stops. More...
#define  DCSR_STOPINTR  (1 << 3)
Stop State (read-only) More...
#define  DCSR_ENDINTR  (1 << 2)
End Interrupt (read / write) More...
#define  DCSR_STARTINTR  (1 << 1)
Start Interrupt (read / write) More...
#define  DCSR_BUSERRINTR  (1 << 0)
Bus Error Interrupt (read / write) More...
#define  DRCMR_MAPVLD  (1 << 7)
Valid Channel mapped. More...
#define  DDADR_STOP  (1 << 0)

Enumerations

enum   DMA_PERIPH_ID {
  DMA_PERIPH_DREQ0 = 0, DMA_PERIPH_DREQ1 = 1, DMA_PERIPH_SSP_4_RX = 2, DMA_PERIPH_SSP_4_TX = 3,
  DMA_PERIPH_BTUART_RX = 4, DMA_PERIPH_BTUART_TX = 5, DMA_PERIPH_FFUART_RX = 6, DMA_PERIPH_FFUART_TX = 7,
  DMA_PERIPH_AC97_MIC = 8, DMA_PERIPH_AC97_MODEM_RX = 9, DMA_PERIPH_AC97_MODEM_TX = 10, DMA_PERIPH_AC97_AUDIO_RX = 11,
  DMA_PERIPH_AC97_AUDIO_TX = 12, DMA_PERIPH_SSP_1_RX = 13, DMA_PERIPH_SSP_1_TX = 14, DMA_PERIPH_SSP_2_RX = 15,
  DMA_PERIPH_SSP_2_TX = 16, DMA_PERIPH_STUART_RX = 19, DMA_PERIPH_STUART_TX = 20, DMA_PERIPH_MMC_RX = 21,
  DMA_PERIPH_MMC_TX = 22, DMA_PERIPH_USB_ENDPOINT_0 = 24, DMA_PERIPH_USB_ENDPOINT_A = 25, DMA_PERIPH_USB_ENDPOINT_B = 26,
  DMA_PERIPH_USB_ENDPOINT_C = 27, DMA_PERIPH_USB_ENDPOINT_D = 28, DMA_PERIPH_USB_ENDPOINT_E = 29, DMA_PERIPH_USB_ENDPOINT_F = 30,
  DMA_PERIPH_USB_ENDPOINT_G = 31, DMA_PERIPH_USB_ENDPOINT_H = 32, DMA_PERIPH_USB_ENDPOINT_I = 33, DMA_PERIPH_USB_ENDPOINT_J = 34,
  DMA_PERIPH_USB_ENDPOINT_K = 35, DMA_PERIPH_USB_ENDPOINT_L = 36, DMA_PERIPH_USB_ENDPOINT_M = 37, DMA_PERIPH_USB_ENDPOINT_N = 38,
  DMA_PERIPH_USB_ENDPOINT_P = 39, DMA_PERIPH_USB_ENDPOINT_Q = 40, DMA_PERIPH_USB_ENDPOINT_R = 41, DMA_PERIPH_USB_ENDPOINT_S = 42,
  DMA_PERIPH_USB_ENDPOINT_T = 43, DMA_PERIPH_USB_ENDPOINT_U = 44, DMA_PERIPH_USB_ENDPOINT_V = 45, DMA_PERIPH_USB_ENDPOINT_W = 46,
  DMA_PERIPH_USB_ENDPOINT_X = 47, DMA_PERIPH_BASEBAND_1_RX = 48, DMA_PERIPH_BASEBAND_1_TX = 49, DMA_PERIPH_BASEBAND_2_RX = 50,
  DMA_PERIPH_BASEBAND_2_TX = 51, DMA_PERIPH_BASEBAND_3_RX = 52, DMA_PERIPH_BASEBAND_3_TX = 53, DMA_PERIPH_BASEBAND_4_RX = 54,
  DMA_PERIPH_BASEBAND_4_TX = 55, DMA_PERIPH_BASEBAND_5_RX = 56, DMA_PERIPH_BASEBAND_5_TX = 57, DMA_PERIPH_BASEBAND_6_RX = 58,
  DMA_PERIPH_BASEBAND_6_TX = 59, DMA_PERIPH_BASEBAND_7_RX = 60, DMA_PERIPH_BASEBAND_7_TX = 61, DMA_PERIPH_USIM_RX = 62,
  DMA_PERIPH_USIM_TX = 63, DMA_PERIPH_SSP_3_RX = 66, DMA_PERIPH_SSP_3_TX = 67, DMA_PERIPH_TPM_RX = 71,
  DMA_PERIPH_TPM_TX_1 = 72, DMA_PERIPH_TPM_TX_2 = 73, DMA_PERIPH_DREQ2 = 74, DMA_PERIPH_USIM_2_RX = 91,
  DMA_PERIPH_USIM_2_TX = 92, DMA_PERIPH_MMC_2_RX = 93, DMA_PERIPH_MMC_2_TX = 94, DMA_PERIPH_AC97_SURROUND_TX = 95,
  DMA_PERIPH_CENTRE_LFE_TX = 96, DMA_PERIPH_NAND_DATA = 97, DMA_PERIPH_NAND_CMD = 99, DMA_PERIPH_MMC_3_RX = 100,
  DMA_PERIPH_MMC_3_TX = 101, DMA_PERIPH_MEM2MEM = 255, DMA_PERIPH_FREE = -1
}
DMA peripheral device DRCMR IDs. More...
enum   DMA_CHANNEL_PRIORITY { DMA_PRIORITY_HIGH = 0, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_LOW, DMA_PRIORITY_LOWEST }
DMAC Channel Allocation Priority. More...

Functions

void  DMAGetLibVersion (DWORD *pVerMaj, DWORD *pVerMin, DWORD *pBuild)
Initialisation. More...
void  DMAInit (void)
Initializes the DMA Library. More...
void  DMADeInit (void)
De-Initializes the DMA Library. More...
DWORD  DMAAllocChannel (DWORD periph)
DMA Channel Management. More...
DWORD  DMAAllocChannelEx (DWORD periph, DWORD priority)
void  DMAReleaseChannel (DWORD chan)
void  DMAReleaseDevice (DWORD periph)
void  DMASetChannelUsage (DWORD chan, CHAR *szChanUsage, DWORD cBytes)
DWORD  DMAGetChannelUsage (DWORD chan, CHAR *szChanUsage, DWORD cBytes)
DMA Preparation
BOOL  DMACreateTransferDescriptors (DWORD sadr, DWORD tadr, DWORD len, DWORD flags, BOOL loop, MEM_T *pMem)
BOOL  DMADestroyTransferDescriptors (MEM_T *pMem)
BOOL  DMAAllocBuffer (MEM_T *pMem, DWORD size)
BOOL  DMAFreeBuffer (MEM_T *pMem)
DMA Real Time Control
DWORD  DMAStartTransferEx (DWORD chan, MEM_T *pMem, DWORD flags, BOOL block)
void  DMAStartShortTransfer (DWORD chan, DWORD sadr, DWORD tadr, DWORD len, DWORD cmd, DWORD csr)
DWORD  DMAStartShortTransferEx (DWORD chan, DWORD sadr, DWORD tadr, DWORD len, DWORD cmd, DWORD csr, BOOL block)
void  _DMAStartTransfer (DWORD chan, MEM_T *pMem, DWORD flags)
void  DMAWaitTransferEnd (DWORD chan)
void  DMAStopTransfer (DWORD chan)
BOOL  DMAGetTrgSrcAdd (DWORD chan, DWORD *dtadr, DWORD *dsadr)
Get current Target and Source address.
. More...
DWORD  DMAGetLen (DWORD chan)

Macro Definition Documentation

#define DCMD_ADDRMODE   (1 << 23)

Addressing Mode.

#define DCMD_BSIZE16   (2 << 16)
#define DCMD_BSIZE32   (3 << 16)
#define DCMD_BSIZE8   (1 << 16)
#define DCMD_BWIDTH16   (2 << 14)
#define DCMD_BWIDTH32   (3 << 14)
#define DCMD_BWIDTH8   (1 << 14)
#define DCMD_CIF_DMA   (1 << 27)

Create a PXA3xx CIF descriptor.

#define DCMD_CMPEN   (1 << 25)

Descriptor Compare Enable.

#define DCMD_ENDIRQEN   (1 << 21)

End Interrupt Enable.

#define DCMD_FLOWSRC   (1 << 29)

Source Flow Control.

#define DCMD_FLOWTRG   (1 << 28)

Target Flow Control.

#define DCMD_FLYBYS   (1 << 20)

Fly-By Source (PXA270 only)

#define DCMD_FLYBYT   (1 << 19)

Fly-By Target (PXA270 only)

#define DCMD_INCSRCADDR   (1 << 31)

Source Address Increment.

#define DCMD_INCTRGADDR   (1 << 30)

Target Address Increment.

#define DCMD_LENGTH   0x01fff

Length of Transfer in Bytes (MASK)

#define DCMD_STARTIRQEN   (1 << 22)

Start Interrupt Enable.

#define DCSR_BUSERRINTR   (1 << 0)

Bus Error Interrupt (read / write)

#define DCSR_CLRCMPST   (1 << 24)

Clear Descriptor Compare Status.

#define DCSR_CMPST   (1 << 10)

Descriptor Compare Status.

#define DCSR_ENDINTR   (1 << 2)

End Interrupt (read / write)

#define DCSR_EORINT   (1 << 9)

End of Receive.

#define DCSR_EORIRQEN   (1 << 28)

End-of-Receive Interrupt Enable.

#define DCSR_EORJMPENT   (1 << 27)

Jump to next Descriptor on End-of-Receive.

#define DCSR_EORSTOPEN   (1 << 26)

Stop Channel on End-of-Receive.

#define DCSR_NODESC   (1 << 30)

No-Descriptor Fetch (read / write)

#define DCSR_RASINTR   (1 << 4)

Request after Channel Stops.

#define DCSR_REQPEND   (1 << 8)

Request Pending (read-only)

#define DCSR_RUN   (1 << 31)

Run Bit (read / write)

#define DCSR_SETCMPST   (1 << 25)

Set Descriptor Compare Status.

#define DCSR_STARTINTR   (1 << 1)

Start Interrupt (read / write)

#define DCSR_STOPINTR   (1 << 3)

Stop State (read-only)

#define DCSR_STOPIRQEN   (1 << 29)

Stop Interrupt Enable (when the descriptor is done) (read / write)

#define DDADR_STOP   (1 << 0)
#define DMA_MAX_CHAN   32

number of available DMA channels

#define DMA_SHARED_FILENAME   (TEXT("ColibriDmaGlobals"))

Memory mapped filename used by the DMALib for interprocess sharing of DMA data structures.

#define DMA_USAGE_LEN   32

maximum string length for a descriptive text (DMA channel usage)

#define DMA_VER_BUILD   1
#define DMA_VER_MAJ   1
#define DMA_VER_MIN   3
#define DRCMR_MAPVLD   (1 << 7)

Valid Channel mapped.

#define PERIPH_CIF1   (68)
#define PERIPH_CIF2   (69)
#define PERIPH_CIF3   (70)
#define PERIPH_SSP1RX   (13)
#define PERIPH_SSP1TX   (14)
#define PERIPH_SSP2RX   (15)
#define PERIPH_SSP2TX   (16)
#define PERIPH_SSP3RX   (66)
#define PERIPH_SSP3TX   (67)
#define PERIPH_SSP4RX   (71)
#define PERIPH_SSP4TX   (72)

Enumeration Type Documentation

DMAC Channel Allocation Priority.

Enumerator
DMA_PRIORITY_HIGH
DMA_PRIORITY_MEDIUM
DMA_PRIORITY_LOW
DMA_PRIORITY_LOWEST

DMA peripheral device DRCMR IDs.

Enumerator
DMA_PERIPH_DREQ0
DMA_PERIPH_DREQ1
DMA_PERIPH_SSP_4_RX
DMA_PERIPH_SSP_4_TX
DMA_PERIPH_BTUART_RX
DMA_PERIPH_BTUART_TX
DMA_PERIPH_FFUART_RX
DMA_PERIPH_FFUART_TX
DMA_PERIPH_AC97_MIC
DMA_PERIPH_AC97_MODEM_RX
DMA_PERIPH_AC97_MODEM_TX
DMA_PERIPH_AC97_AUDIO_RX
DMA_PERIPH_AC97_AUDIO_TX
DMA_PERIPH_SSP_1_RX
DMA_PERIPH_SSP_1_TX
DMA_PERIPH_SSP_2_RX
DMA_PERIPH_SSP_2_TX
DMA_PERIPH_STUART_RX
DMA_PERIPH_STUART_TX
DMA_PERIPH_MMC_RX
DMA_PERIPH_MMC_TX
DMA_PERIPH_USB_ENDPOINT_0
DMA_PERIPH_USB_ENDPOINT_A
DMA_PERIPH_USB_ENDPOINT_B
DMA_PERIPH_USB_ENDPOINT_C
DMA_PERIPH_USB_ENDPOINT_D
DMA_PERIPH_USB_ENDPOINT_E
DMA_PERIPH_USB_ENDPOINT_F
DMA_PERIPH_USB_ENDPOINT_G
DMA_PERIPH_USB_ENDPOINT_H
DMA_PERIPH_USB_ENDPOINT_I
DMA_PERIPH_USB_ENDPOINT_J
DMA_PERIPH_USB_ENDPOINT_K
DMA_PERIPH_USB_ENDPOINT_L
DMA_PERIPH_USB_ENDPOINT_M
DMA_PERIPH_USB_ENDPOINT_N
DMA_PERIPH_USB_ENDPOINT_P
DMA_PERIPH_USB_ENDPOINT_Q
DMA_PERIPH_USB_ENDPOINT_R
DMA_PERIPH_USB_ENDPOINT_S
DMA_PERIPH_USB_ENDPOINT_T
DMA_PERIPH_USB_ENDPOINT_U
DMA_PERIPH_USB_ENDPOINT_V
DMA_PERIPH_USB_ENDPOINT_W
DMA_PERIPH_USB_ENDPOINT_X
DMA_PERIPH_BASEBAND_1_RX
DMA_PERIPH_BASEBAND_1_TX
DMA_PERIPH_BASEBAND_2_RX
DMA_PERIPH_BASEBAND_2_TX
DMA_PERIPH_BASEBAND_3_RX
DMA_PERIPH_BASEBAND_3_TX
DMA_PERIPH_BASEBAND_4_RX
DMA_PERIPH_BASEBAND_4_TX
DMA_PERIPH_BASEBAND_5_RX
DMA_PERIPH_BASEBAND_5_TX
DMA_PERIPH_BASEBAND_6_RX
DMA_PERIPH_BASEBAND_6_TX
DMA_PERIPH_BASEBAND_7_RX
DMA_PERIPH_BASEBAND_7_TX
DMA_PERIPH_USIM_RX
DMA_PERIPH_USIM_TX
DMA_PERIPH_SSP_3_RX
DMA_PERIPH_SSP_3_TX
DMA_PERIPH_TPM_RX
DMA_PERIPH_TPM_TX_1
DMA_PERIPH_TPM_TX_2
DMA_PERIPH_DREQ2
DMA_PERIPH_USIM_2_RX
DMA_PERIPH_USIM_2_TX
DMA_PERIPH_MMC_2_RX
DMA_PERIPH_MMC_2_TX
DMA_PERIPH_AC97_SURROUND_TX
DMA_PERIPH_CENTRE_LFE_TX
DMA_PERIPH_NAND_DATA
DMA_PERIPH_NAND_CMD
DMA_PERIPH_MMC_3_RX
DMA_PERIPH_MMC_3_TX
DMA_PERIPH_MEM2MEM
DMA_PERIPH_FREE

Function Documentation

void _DMAStartTransfer ( DWORD  chan,
MEM_T *  pMem,
DWORD  flags
)

Start a DMA transfer which was previously setup using DMACreateTransferDescriptors().
Needed to be renamed because in Wince 6.0 we have a naming conflict with a CEDDK function!!

Parameters
[in] chan DMA channel number
[in] pMem Physical and virtual address of the descriptor
[in] flags Flags for the DMA Control/Status Register
BOOL DMAAllocBuffer ( MEM_T *  pMem,
DWORD  size
)

Allocate physical memory that can be used as source or target for DMA transfers.

Parameters
[out] pMem Physical and virual address of the allocated memory
[in] size Required memory size in bytes
Return values
TRUE Success
FALSE Error occured
DWORD DMAAllocChannel ( DWORD  periph )

DMA Channel Management.

Searches for a free channel and allocates it.

Parameters
[in] periph DMA peripheral device DRCMR ID
Return values
-1 No free channel found.
>=0 Allocated DMA channel number
Deprecated:
Obsolete fuction!
DWORD DMAAllocChannelEx ( DWORD  periph,
DWORD  priority
)

Searches for a free channel with specific priority and allocates it.

Parameters
[in] periph DMA peripheral device DRCMR ID
[in] priority Requested Priority. See DMA_CHANNEL_PRIORITY
Return values
-1 No free channel found for the requested priority.
>=0 Allocated DMA channel number.
BOOL DMACreateTransferDescriptors ( DWORD  sadr,
DWORD  tadr,
DWORD  len,
DWORD  flags,
BOOL  loop,
MEM_T *  pMem
)

Create DMA Transfer descriptor.
NOTE: TransferDescriptors in RAM are only required for transfers of 8kB or more.

Parameters
[in] sadr Source address
[in] tadr Target address
[in] len Length of Transfer in Bytes, see also DMA Command Registers
[in] flags Flags for the DMA Command Registers
[in] loop TRUE: DMA descriptor chain is a loop
[out] pMem Physical and virtual address of the descriptor
Return values
TRUE Success
FALSE Error occured
void DMADeInit ( void  )

De-Initializes the DMA Library.

BOOL DMADestroyTransferDescriptors ( MEM_T *  pMem )

Release memory reserved for the transfer descriptor.
NOTE: TransferDescriptors in RAM are only required for transfers of 8kB or more.

Parameters
[in,out] pMem Physical and virtual address of the descriptor
Return values
TRUE Success
FALSE Error occured
BOOL DMAFreeBuffer ( MEM_T *  pMem )

Free the physical memory that was allocated by DMAAllocBuffer()

Parameters
[in,out] pMem Physical and virtual address of the allocated memory
Return values
TRUE Success
FALSE Error occured
DWORD DMAGetChannelUsage ( DWORD  chan,
CHAR *  szChanUsage,
DWORD  cBytes
)

Get the descriptive text for what a DMA channel is used for.

Parameters
[in] chan DMA channel number
[out] szChanUsage Descriptive Text (Zero-terminated ASCII string)
[in] cBytes Maximum allowed String Length in Bytes
Return values
DWORD Actually returned string length.
DWORD DMAGetLen ( DWORD  chan )

Get number of bytes already transferred.

Parameters
[in] chan DMA channel number
Return values
DWORD Number of bytes already transferred.
void DMAGetLibVersion ( DWORD *  pVerMaj,
DWORD *  pVerMin,
DWORD *  pBuild
)

Initialisation.

Returns the library Version.

Parameters
[out] pVerMaj Returns the major version number. Set this parameter to NULL if not required.
[out] pVerMin Returns the minor version number. Set this parameter to NULL if not required.
[out] pBuild Returns the build number. Set this parameter to NULL if not required.
BOOL DMAGetTrgSrcAdd ( DWORD  chan,
DWORD *  dtadr,
DWORD *  dsadr
)

Get current Target and Source address.
.

Parameters
[in] chan DMA channel number
[out] dtadr Target address
[out] dsadr Source address
Return values
TRUE Success
FALSE Error occured
void DMAInit ( void  )

Initializes the DMA Library.

void DMAReleaseChannel ( DWORD  chan )

Release/free DMA Channel

Parameters
[in] chan DMA channel number. Remarks: ATTENTION! Parameter changed to channel number.
Used to be peripheral device ID which is inappropriate.
See new Function: DMAReleaseDevice.
void DMAReleaseDevice ( DWORD  periph )

Releases Device allocated DMA Channel.

Parameters
[in] periph DMA peripheral device DRCMR ID
void DMASetChannelUsage ( DWORD  chan,
CHAR *  szChanUsage,
DWORD  cBytes
)

Set a descriptive text for what a DMA channel is used for.

Parameters
[in] chan DMA channel number
[in] szChanUsage Descriptive Text (Zero-terminated ASCII string)
[in] cBytes String Length in Bytes
void DMAStartShortTransfer ( DWORD  chan,
DWORD  sadr,
DWORD  tadr,
DWORD  len,
DWORD  cmd,
DWORD  csr
)

Start DMA transfer non descriptor mode.
NOTE: This can only be used for transfers < 8kB

Parameters
[in] chan DMA channel number
[in] sadr Source address
[in] tadr Target address
[in] len Length of Transfer in bytes (max. 8191)
[in] cmd Flags for the DMA Command Registers
[in] csr Flags for the DMA Control/Status Register
DWORD DMAStartShortTransferEx ( DWORD  chan,
DWORD  sadr,
DWORD  tadr,
DWORD  len,
DWORD  cmd,
DWORD  csr,
BOOL  block
)

Start DMA transfer non-descriptor mode.
NOTE: This can only be used for transfers < 8Kb

Parameters
[in] chan DMA channel number
[in] sadr Source address
[in] tadr Target address
[in] len Length of Transfer in bytes (max. 8191)
[in] cmd Flags for the DMA Command Registers
[in] csr Flags for the DMA Control/Status Register
[in] block TRUE: function returns after DMA is finished
FALSE: function returns immediately
Return values
TRUE Success
FALSE Timeout detected
DWORD DMAStartTransferEx ( DWORD  chan,
MEM_T *  pMem,
DWORD  flags,
BOOL  block
)

Start a DMA transfer which was previously setup using DMACreateTransferDescriptors().

Parameters
[in] chan DMA channel number
[in] pMem Physical and virtual address of the descriptor
[in] flags Flags for the DMA Command Registers
[in] block TRUE=function returns after DMA is finished
FALSE= function returns immediately
Return values
TRUE Success
FALSE Timeout detected
void DMAStopTransfer ( DWORD  chan )

Early stop DMA transfer

Parameters
[in] chan DMA channel number
void DMAWaitTransferEnd ( DWORD  chan )

Wait until DMA transfer is finished

Parameters
[in] chan DMA channel number