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External Memory Bus

 

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The Colibri modules provide an external memory bus.

Please consult the Marvell PXA Datasheet for a complete documentation. In case you are not sure about your design you can contact our support. We also provide schematic reviews to support your hardware development.

Module differences

Colibri PXA270

  • 32 bit bus with dedicated data and address lines
  • 26 address lines available
  • 3 External Chip Selects available. (Different timings possible)

Colibri PXA3xx

  • 16 bit bus with dedicated data and address lines or multiplexed (AA/D) bus
  • 12 dedicated address lines available
  • 3 External Chip Selects available (Same timings for all CS)

Memory Interface Types

There are two different modes used to connect external devices, the SRAM and the VLIO mode.
The main differences between these 2 modes are the timings, the ready signal, and the behavior of the nOE signal.
The synchronous memory interface is not supported on the Colibri modules.

Differences SRAM vs. VLIO Mode

Ready Signal

This signal is only used in the VLIO mode. The signal can be used by external device to delay a read access. However it is not required to use this signal. If not used keep it high.
If you keep this signal low, the memory bus is blocked. Marvell recommends using a watchdog to prevent the system form hanging if the external device doesn’t release the ready signal.
Important: Do not use this feature on Colibri PXA270 V1.2d and older!

Burst Access

In VLIO mode the nOE signal toggles for each beat of a burst.

Timings

(This chapter focuses only on Colibri PXA3xx modules)

RND and RDF in the MSC Register
  • RDNx

SRAM: Set the DF_nWE assertion time.
VLIO: Setup and hold times in relation to the DF_nWE and DF_nOE signals.

  • RDFx

SRAM: Set the nOE assertion time and to program the read data setup time.
VLIO: nWE and nOE assertion time.

In general, this means the timings o of the VLIO mode are more flexible. Especially the setup and hold times. For details see the Marvell PXA3xx EMTS datasheet.

The timings are depending of the DF_CLK clock. The DF_CLK clock can be set in the Configblock (mult.dfclkdiv).
Please note hat we change the DF_CLK in boot loader Version 3.4!

Control Signals

  • Output enable (nOE) on SODIMM pin 91

Asserted for reads.
In VLIO mode this signal toggles with each beat of a burst in SRAM mode not.

  • Write enable (nWE) on SODIMM pin 89

Colibri PXA3xx: the same signal than on pin 99. This signal is used as write enable for the SRAM and VLIO mode.
Colibri PXA270: This signal is used as write enable in the SRAM mode.

  • Write enable (nPWE)on SODIMM Pin 99

Colibri PXA3xx: This is the same signal than on pin 89. This signal is used as write enable for SRAM and VLIO mode.

Colibri PXA270: This signal is used as write enable in the VLIO mode (and the PC Card interface).

If you need a VLIO interface which is compatible with all modules use SODIMM Pin 99 as write enable.

WARNING: Some of the earlier Colibri PXA3xx modules do not have the write enable on SODIMM pin 99.