The NXP/Freescale VF6xx SoC which is the core of the Colibri VF61 module implements a heterogeneous asymmetric architecture. Besides the main CPU core based on the ARM Cortex-A5 processor, a secondary general purpose ARM Cortex-M4 core is available too. The secondary core typically runs a RTOS optimized for microcontrollers or a bare-metal application. Toradex provides FreeRTOS™, a free professional grade real-time operating system for microcontrollers, along with drivers and several examples which can be used on our Colibri VF61 platform. The FreeRTOS™ port is based on NXP FreeRTOS BSP for i.MX 7.
The FreeRTOS source code is available at: http://git.toradex.com/cgit/freertos-toradex.git/ branch colibri-vf61-m4-freertos-v8
The Cortex-M4 CPU core lives side by side with the Cortex-A5 based primary CPU core. Both CPU complexes have access to the same interconnect and hence have equally access to all peripherals (shared bus topology).
There are several types of memory available. The Cortex-M4 provides local memory (Tightly Coupled Memory, TCM), which is relatively small but can be accessed by the CPU without any latency. There are multiple OCRAM areas (On-Chip RAM, typically SRAM) which are relatively fast as well and slightly larger. The third option is the DDR3 based main memory. From a performance perspective one of the internal areas should be selected whenever possible.
A traditional microcontroller typically has internal NOR flash where the firmware is stored and executed from. This is not the case on Colibri VF61: There is no NOR flash where the firmware can be flashed onto. Instead, the firmware needs to be stored on the mass storage device such as SD-card or the internal NAND flash. The available mass storage devices are not "memory mapped", and hence application can not be executed directly from any of the cores (no eXecuted-In-Place, XIP). Instead, code need to be loaded into one of the available memory sections before the CPU can start executing it.
The Colibri VF61 always boots using the Cortex-A5 core. The core executes the internal boot ROM which typically loads a boot loader such as U-Boot. The boot loader allows loading the firmware from the mass storage device (e.g. NAND flash) into memory, and triggers the Cortex-M4 to start executing the firmware. To upgrade or replace a firmware, one can just replace the firmware binary on the mass storage device.
The two CPU platforms use a different memory layout to access individual sub systems. This table lists some important areas and their memory location for each of the cores side by side. The full list can be found in the Vybrid reference manual.
|Region||Size||Cortex-A5||Cortex-M4 (System Bus)||Cortex-M4 (Code Bus)|
|DDR Address||2048MB (less for M4)||
The FreeRTOS source code is available on our git server. Use git to clone the repository:
# git clone -b colibri-vf61-m4-freertos-v8 git://git.toradex.com/freertos-toradex.git
This table shows how the FreeRTOS BSP source code is structured:
|doc/||NXP/Freescales FreeRTOS BSP Documentation|
|examples/vf6xx_colibri_m4/||Examples ported to Toradex Colibri VF61|
|middleware/multicore/open-amp/||OpenAMP based RPMsg stack (remote messaging framework)|
|platform/||Driver library, startup code and utilities|
|platform/CMSIS/||Cortex Microcontroller Software Interface Standard (CMSIS) ARM Cortex®-M header files, DSP library source|
|platform/devices/VF6XX/linker/||Linker control files for each supported toolchain|
|platform/utilities/||Utilities such as debug console|
|rtos/FreeRTOS/||FreeRTOS Kernel folder|