The Apalis standard provides two SPI interfaces compatible with all modules of the Apalis family.
|MXM3 Pin||Apalis Signal Name||Description|
|225||SPI1_MOSI||Master Output, Slave Input|
|223||SPI1_MISO||Master Input, Slave Output|
|231||SPI2_MOSI||Master Output, Slave Input|
|229||SPI2_MISO||Master Input, Slave Output|
The Colibri standard provides one SPI interface compatible with all modules of the Colibri family.
|SODIMM Pin||Colibri Signal Name||Description|
|86||SSPFRM||SPI Chip Select/ SPI Frame/ SPI Enable Signal|
|90||SSPRXD||SPI Master Input / Slave Output (MISO)|
|92||SSPTXD||SPI Master Output / Slave Input (MOSI)|
The Apalis/Colibri standard SPI interfaces are enabled by default. Most modules offer additional (non-standard) SPI interfaces, to enable these device tree or board file customization are required.
SPI access from user-space is provided through the spidev driver which exports device files under /dev. See Documentation/spi/spidev in the kernel sources for more information.
The following shows a read of an ADC082S021 using the sample code in the kernel sources (Documentation/spi/spidev_test.c) using spidev interface:
# ./spidev_test -D /dev/spidevB.C spi mode: 0 bits per word: 8 max speed: 500000 Hz (500 KHz) 02 E0 00 00 00 00 00 00 02 E0 02 E0 02 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
The Linux kernel already provides drivers for various SPI devices, hence before writing your own driver checking your Linux kernels configuration options and/or searching through the kernel mailing list is best practice.
If you plan to write a SPI device driver you can use the SPI MCP2515 CAN controller driver as an example. The MCP2515 CAN controller is available and connected to the Colibri SPI port on the v3 series of the Colibri Evaulation Board.
By default the regular SPI interface is configured for 3 MHz operation. The sbc4 clock which is four times the SPI clock is configured for 12 MHz operation with pll_p as its parent. As the divider between its parent and sbc4 only supports 7.1 bits (e.g. 7 bits of mantissa and 1 bit of fraction) and pll_p runs at 216 MHz the lowest possible SPI clock in that configuration lays somewhere around 424 kHz. If a lower clock is desired one has to choose another parent clock like clk_m operating at 13 MHz. This allows SPI clocks as low as 25 kHz. In the Linux kernel sources that configuration can be found here.
As follows some clock tree excerpts for a few use-cases:
DEFAULT spidev configuration clk_m on 11 13000000 pll_p on 11 x16.6.. 216000000 sbc4 off 0 18 12000000 MCP2515 CAN configuration clk_m on 11 13000000 pll_p on 11 x16.6.. 216000000 sbc4 off 0 5.5 39272727 => 9.830 MHz measured at SSP_SCLK pin clk_m on 11 13000000 pll_p on 11 x16.6.. 216000000 sbc4 off 0 127.5 1694117 => 423.6 kHz measured at SSP_SCLK pin clk_m on 11 13000000 sbc4 off 0 65 200000 => 50 kHz measured at SSP_SCLK pin