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Peripheral Control on Verdin AM62 Deep Sleep

Introduction​

This article outlines the limitations of using GPIOs during Deep Sleep mode on the Verdin AM62 V1.2 SoM, explaining how internal pull resistors and external loads can cause voltage shifts that may lead to unexpected peripheral behavior. It also provides calculation examples and mitigation strategies.

Problem Description​

Devices controlled by SoM GPIOs may experience unintended state changes when the Verdin AM62 V1.2 transitions to Deep Sleep mode, including resets or unexpected power-on/off events.

During this mode, the output buffers of the GPIO pins are disabled, placing the pins in a High-Z state. To preserve the GPIOs' state in this mode, the SoC’s internal pull-up and pull-down resistors (ranging from 15 kΩ to 30 kΩ) are enabled. These resistors are automatically managed by the SoC's firmware prior to entering Deep Sleep mode. Consequently, the output voltage on the SoM's I/O pins will be affected by the external load's pull-up or pull-down values, as well as by bias currents. This fluctuation may cause a significant voltage drop across the internal resistors.

Refer to the figure below for illustration:

The issue arises when the external pull-up/pull-down resistor conflicts with the internal pull-up/pull-down used to maintain the GPIOs' state during Deep Sleep mode. This conflict can cause the output voltage on the GPIO pins to fall below or exceed the threshold voltages of the peripheral devices, potentially leading to unexpected behavior when the module enters Deep Sleep mode. Furthermore, since the limitation described below also affects the signal CTRL_SLEEP_MOCI#, it hinders the BSP’s ability to drive this signal properly.

Workaround Proposal​

To ensure optimal functionality during Deep Sleep mode with the Verdin AM62 module, it is advisable to estimate the output voltage on the I/O pins under worst-case conditions, considering the internal 30kΩ pull-up or pull-down resistor.

Based on these calculations, take appropriate measures, such as selecting peripheral components with suitable I/O voltage thresholds and low pin bias currents, considering the resistive loads on the pins.

There are two most common scenarios:

  1. An internal pull-up is used to maintain the GPIOs' state during Deep Sleep mode, while an external pull-down resistor is connected. Bias current is flowing into the peripheral's pin.

    The following formula can be used to calculate the SoM pin's voltage:

  2. An internal pull-down is used to maintain the GPIOs' state during Deep Sleep mode, while an external pull-up resistor is connected. Bias current is flowing out of the peripherals pin.

    The following formula can be used to calculate the SoM pin's voltage:

The figure below illustrates the relationship between the output voltage on the SoM I/O pin, external load, and bias current for the first scenario:

The following figure shows the same calculations for the second scenario:

An I²C GPIO expander can be used as an alternative solution to drive the peripherals' reset and power-gating GPIOs during the Deep Sleep state.

Important Notes​

  • Please note that the CTRL_SLEEP_MOCI# pin of the Verdin AM62 SoM already has a 100k pull-down resistor installed on the module. For better reliability, this signal can be buffered with a logic buffer IC.

  • When selecting the value of RLoad, keep in mind that the bias current on the peripheral IC inputs can flow in both directions, leading to a significant voltage drop across RLoad when the AM62 SoC is in the reset state and the peripherals stay powered on. If the input pins of the peripheral IC have a high leakage current and RLoad is also large, the resulting voltage drop may exceed the threshold voltage of the IC input, potentially affecting the circuit functionality during the AM62 SoC reset state.

For additional information on this topic, refer to:

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