This library manages the SPI interfaces via DMA.
SPILib supports up to 5 SPI ports on Colibri modules.
For SPILib to function correctly, it is necessary to disable Dynamic Frequecncy Switching (DFS) - See here. In Library revision V5.0 and higher, this is not required anymore, the frequency is automatically increased between SpiInit and SpiDeinit.
For data packets smaller than the FIFO (32 frames on the T20/T30, it is recommended to use the polling mode functions instead of the DMA based functions. They require less overhead to setup a transfer and therefore provide shorter latencies.
|30/10/2014||V5.3||Fix issue on T20/T30 modules: Small SPI transfers using DMA caused the application to freeze.
Fix issue on T20/T30 modules: SPI transfers using DMA caused the application to freeze, if transfer size was not a multiple of 4.
|27/05/2014||V5.2||Non-standard SPI pin configurations can now be defined as GPIO numbers instead of SODIMM pins. This is to support on-module SPI channels, e.g. for the Apalis on-module CAN controllers
Adjust default SPI pin configurations for Apalis
|15/04/2014||V5.1||Add TegSpiSetWaitMethod() to choose between interrput-driven and busyLoop waiting
Use DMA-like SPI control method even in non-DMA mode to prevent possible data loss of received data.
Remove deprecated functions TegWriteSPIUnpacdked() and TegReadSPIUnpacked()
Fix issue that caused a data abort when calling SPIInit() the 2nd time
|11/03/2014||V5.0||Fix bit rate calculation
Pre-allocate memory for DMA, instead of allocating it for each transfer
Fix pin initialization
|23/09/2013||V4.1||Change default SDK to Colibri600 / Added support for T30's SPI5 and SPI6|
|12/08/2013||V4.0.1||Improved performance of SPIReadWritePolling(), SPIReadPolling() and SPIWritePolling() on Tegra processors|