| HAR-8290||Known Issue||The LED status signals of the on-module Ethernet PHY are swapped on the Verdin Development Board||Verdin Development Board V1.1A|
Verdin Development Board V1.0B
Customer Impact: The roles of the Ethernet link and activity LEDs are swapped (the wrong Ethernet LED is turned on or is blinking).
Description: The KSZ9131 Ethernet PHY on the Verdin modules has two LED outputs (ETH_1_LED_1 and ETH_1_LED_2) which are used for indicating the link and activity statuses on the bus.
These LEDs are available on pin 235 and 237 of the module edge connector, respectively. ETH_1_LED_1 (pin 235) is intended to indicate the activity status, while ETH_1_LED_2 (pin 237) is intended to indicate the link status.
On the PCB versions 1.0 and 1.1, these two signals are swapped.
In the next revision of the carrier board PCB, the connections will be corrected.
In the Verdin Development Board datasheet, the corrected connections are shown.
Workaround: For custom carrier board designs, the correct LED connections should be implemented.
A potential workaround could be flipping the roles and behavior of the LED outputs of the on-module Ethernet PHY in software. However, this is not supported by the related driver.
| HAR-8016||Known Issue||CSI_1_MCLK Voltage Level is not 3.3V ||Verdin Development Board 1.0A|
Verdin Development Board V1.1A
Customer Impact: In case a MIPI CSI-2 camera requires the CSI_1_MCLK signal (pin #12 of X47), and in case it requires this signal to be at 3.3V level, then the current voltage level of the signal won't be compatible with the camera.
Description: On the MIPI CSI-2 interface used on the Verdin Development Board V1.1A, all of the single-ended signals are at 3.3V level, except for the CSI_1_MCLK signal (pin #12 of X47), which is at 1.8V level.
Workaround: In case a MIPI CSI-2 camera requires the CSI_1_MCLK signal (pin #12 of X47), and in case it requires this signal to be at 3.3V level, it could be level shifted on custom carrier boards.
| HAR-7206||Known Issue||Series capacitor values are too small for the audio codec’s speaker output to be used in a stereo setup||Verdin Development Board V1.1A|
Customer Impact: The audio output is significantly attenuated or not audible at all when the audio codec's speaker output is used in combination with external speakers connected in a stereo setup. The issue does not affect the speaker output when the external speakers are connected in a mono setup.
Description: The audio codec featured on the Verdin Development Board V1.1 includes an integrated speaker driver. The Verdin Development Board V1.1 provides two operating modes for the audio codec speaker output: mono and stereo. In a mono setup, one or two external speakers are connected as a Bridge Tied Load (BTL) to the connectors X28 and/or X29. In this setup, the speaker output should work fine. In a stereo setup, two external speakers are connected to the connector X13. In this case, one end of each speaker’s coil is connected to the common ground pin (GND), the other ends are connected to the audio codec IC through the capacitors C182 or C183, respectively. The capacitors C182 (1uF) and C183 (1uF), in conjunction with the speaker’s impedance (8Ohm), form high-pass filters. The cut-off frequency of the high-pass filters is around 20 kHz. This frequency is at the upper edge of the audible frequency range, and lower frequencies are attenuated/filtered out by the aforementioned high-pass filter.
Workaround: A partial workaround has already been applied to the Verdin Development Board V1.1A: 0Ohm resistors have been assembled instead of the capacitors C182, C183. To complete the workaround, external capacitors connected in series with the external speakers are required (see Figure 3). The exact values of the capacitors depend on the desired cut-off frequency and the impedance of the speakers. Some applications may not require the complete audible frequency range of approx. 20Hz – 20Hz to be available. The low-frequency limit is 100Hz for many low-power speakers, so it may be unnecessary to go below this cut-off frequency. For 8Ohm speakers, our recommendation is to use either 220uF series capacitors for a cut-off frequency of approx. 90Hz or 470uF for 42Hz respectively (minimum 6.3V rated in both cases). Please check Errata #6 in the Verdin Development Board errata for more information.
| HAR-6600||Known Issue||Ethernet PHY address strapping resistor for configuring PHYAD2 missing||Verdin Development Board V1.0B||Verdin Development Board V1.1A|
Customer Impact: In combination with the Verdin iMX8M Plus, the Ethernet PHY on the carrier board (which is connected to the RGMII interface of the SoM) gets strapped to address 0b00011 rather than the intended 0b00111. This address is not compatible with the default address configuration used in applicable Toradex software, causing the 2nd Ethernet interface of the carrier board to be non- functional. The strapped value and the resulting PHY address - in combination with future Verdin modules - may be different.
Description: The last three bits of the PHY address are strapped by the PHYAD0, PHYAD1, and PHYAD2 pin. PHYAD0 and PHYAD1 are located on the LED output signals, which are strapped correctly. PHYAD2 is located on the RXC pin of the PHY (ETH_2_RGMII_RXC signal). The strapping resistors R188 and R189 are both missing in the BOM. Intended by design is to strap the signal high by assembling R188. Since both strapping resistors are missing, the strapping value is dictated by the module’s behavior of the ETH_2_RGMII_RXC signal during the enabling of the Ethernet power rails. The Ethernet power rails are enabled on the carrier board by the PWR_CTRL_4 signal. The Verdin iMX8M Plus has a weak pull-down enabled on the ETH_2_RGMII_RXC by default. Therefore, the PHY address gets strapped to 0b00011 rather than the intended 0b00111. In this case, the module can only communicate over the MDIO interface with the PHY if the driver changes the address to 0b00011.
Workaround: The best workaround is to populate R188 with a 10kΩ resistor. The resistor is a 0603 type. See Errata #5 of the Verdin Development Board errata for more information.
| HAR-3935||Known Issue||CTRL_FORCE_OFF_MOCI# is pulled-up to wrong voltage rail||Verdin Development Board V1.0B||Verdin Development Board V1.1A|
Customer Impact: During a reset cycle (software or button initiated), the CTRL_PWR_EN_MOCI# signal can go low for power cycling the peripherals on the carrier board. This is disabling also the +V1.8_SW which means the CTRL_FORCE_OFF_MOCI# goes low and triggers the kill input of IC16. IC16 will then kill the main power of the module. This means resetting the module can cause an unintentionally power-off of the system.
Description: According to the Verdin specifications, the CTRL_FORCE_OFF_MOCI# is an open-drain output of the module which is 5V tolerant and requires a pull-up resistor on the carrier board. On the Verdin Development Board V1.0B, the CTRL_FORCE_OFF_MOCI# is pulled up to the +V1.8_SW rail. Unfortunately, this rail is switched by the CTRL_PWR_EN_MOCI# signal. During a reset cycle (software or button initiated), the CTRL_PWR_EN_MOCI# signal can go low for power cycling the peripherals on the carrier board. This is disabling also the +V1.8_SW which means the CTRL_FORCE_OFF_MOCI# goes low and triggers the kill input of IC16. IC16 will then kill the main power of the module. This means resetting the module can cause an unintentionally power-off of the system.
Workaround: Removing R80 disables the CTRL_FORCE_OFF_MOCI# signal on the Verdin Development Board.
However, this disables the “kill-feature” entirely. Therefore, after a shutdown, the supplies are not turned off which prevents the system to be turned on by using the power button. For turning on the system, either power cycle the whole board or turn off the main 3.3V rail on the carrier board by pressing the power button >3s. Besides this inconvenience, the modification is compatible with all Verdin module versions.
| HAR-3379||Known Issue||Missing pull-up resistor on the WAKE1_MICO# signal||Verdin Development Board V1.0B||Verdin Development Board V1.1A|
Description: The Pull-up resistor is missing on the WAKE1_MICO# signal.
Workaround: It is recommended to enable the SoM’s internal pull-up of the pin connected to this signal.
| HAR-3274||Known Issue||Inconsistency concerning the position of general-purpose LEDs and the order of related signals on connector X38||Verdin Development Board V1.0B||Verdin Development Board V1.1A|
Description: The position of LED21, LED22, LED23, LED24 in the general-purpose LEDs and Switches area is not consistentwith the order of related signals available on the connector X38.
Workaround: Users should check table 220.127.116.11.5 of the product datasheet to avoid confusion when using this product feature.
| HAR-3252||Known Issue||SDIO failing when clock is higher than 134MHz||Verdin Development Board 1.0A|
Verdin Development Board V1.0B
|Verdin Development Board V1.1A|
Description: SDIO interface is failing when clock is chosen higher than 134MHz
Workaround: Use 'max-frequency' in the devicetree to limit the clock to below equal 134MHz.