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Heterogeneous Multi-core Processing Overview

Introduction​

Heterogeneous Multi-core Processing (HMP) on Toradex SoMs enables you to pair a high-performance application processor running Linux with one or more low-power Cortex-M/Cortex-R real-time cores. This architecture offloads time-critical or deterministic tasks (e.g. sensor handling, motor control) to the Cortex-M/Cortex-R cores, while the Cortex-A handles higher-level functions, typically running a fully featured OS (like Embedded Linux, Torizon, Android or QNX, among others) - enabling both high throughput and real-time responsiveness.

HMP is also known as Asymmetric Multiprocessing (AMP), Asymmetric MCU Clustering, Dual-Core MCU, Domain-specific MCU Islands or Co-processor Offload.

Glossary​

  • MCUXpresso SDK: NXP's software development kit for Cortex-M, providing libraries, headers and example projects.
  • U-Boot: The bootloader used on Toradex SoMs; supports commands to load binaries into the Cortex-M/R core, such as ext4load.
  • RemoteProc: Linux kernel framework to boot and control remote processors (Cortex-M/R) from the main CPU.
  • RPMsg: IPC protocol built on top of RemoteProc for message-based communication between Linux and Cortex-M/R.
  • Shared Memory: Memory region mapped into both domains for fast data exchange.
  • JTAG: Hardware interface for debugging and programming embedded cores.

Getting started with HMP​

The below steps are relevant for evaluation and testing purposes:

  1. Set up resource sharing between the cores:

    1. Configure your pins: Specify the pin function and settings to share control over the physical pins across the Cortex-M/Cortex-R and Cortex-A. Refer to the Pinmuxing Guide for detailed information.

    2. Configure HMP memory areas: Review the memory map on your Toradex SoM to allocate regions for firmware, data, and shared buffers. Refer to our Memory Areas on Toradex SoMs Article for detailed information.

  2. Configure your host machine to build firmware binary for your Cortex-M/Cortex-R:

    1. On SoMs using NXP chips: Install and configure the MCUXpresso IDE or CLI toolchain to build your Cortex-M firmware. Refer to our Setting-up SDK toolchain guide for detailed instructions.

    2. On SoMs using TI chips: Install and configure the MCU-PLUS-SDK to build your Cortex-R firmware. Refer to the dedicated section on our Cortex-R AM62 Guide for detailed instructions.

  3. Load binaries into the Cortex-M/Cortex-R: Deploy and run your binary to the target hardware. Refer to our How to Load Compiled Binaries into Cortex-M guide for detailed instructions.

  4. Set up communication with Cortex-A:

    1. Using RPMsg: Initialize RPMsg channels in both Linux and your firmware to exchange control messages and data. Refer to our How to Use RemoteProc guide for detailed instructions.

    2. Using Shared Memory: Reserve a shared memory region for bulk data exchange (e.g. sensor streams, logs) between Cortex-A and Cortex-M/Cortex-R. Refer to our Cortex-M Shared Memory guide for detailed instructions.

  5. Boot and manage the Cortex-M/Cortex-R via RemoteProc: Enable and control core power-up/shutdown from Linux using the remoteproc framework.

  6. Debug with JTAG: Connect via JTAG to step through firmware, set breakpoints or inspect memory on the Cortex-M/Cortex-R. Refer to Cortex-M JTAG Debugging guide for detailed instructions.

  7. Run a Hello World demo: Follow the How to Run Hello World on the Cortex-M guide to verify your setup and toolchain.

info

After following the above steps and validating the integration between HMP infrastructure and your software, you will need to follow additional steps to develop production-ready images. Please note that those steps are not instructed on the Toradex Developer Website.

Having trouble?​

Please check out our Community Forum for additional support.



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