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Device Tree Customization


A Device Tree is a data structure describing a system's hardware. Some hardware is "discoverable" by design (e.g. PCI buses or USB buses) while some is not (notably memory-mapped peripherals). In the latter case, an operating system executable (the OS kernel) is often hard-coded for one device type. To make an operating system portable across different devices, a description of the layout of each supported hardware configuration is required to ensure the correct drivers and configuration are used. The ARM world is very heterogeneous, each SoC vendor and each board vendor wire their hardware a bit differently. In some other architectures (e.g. x86), there is a standard interface between the board firmware (BIOS) and the operating system to communicate the hardware layout - for instance, ACPI on x86. To overcome this lack of hardware description, the ARM Linux Kernel uses device trees as the preferred format of hardware description beginning around kernel version ~3.2. Prior to this change, all details of how the hardware was wired was part of the platform/machine layer and hard-coded in C structs. This became complicated as more and more ARM SoC vendors and boards appeared. More in-depth information is available in the presentation of Thomas Petazzoni about device trees.

The device-tree is not only a data structure that describes the SoC's internal memory-mapped peripherals, but it also allows us to describe the whole board. Toradex, therefore, creates device trees for each module as well as each carrier board (given that the modules Linux BSP supports device tree, see table below). However, especially if a custom carrier board is built, it is likely that you as a customer need to modify the device tree too. This article provides information on how to do that.

Some of our Linux BSPs make use of device tree enabled Linux kernels. The device trees are part of the Linux kernel source code and located in the arch/arm/boot/dts/ folder. For instructions on how to obtain the Linux source code for each module, refer to the article Build U-Boot and Linux Kernel from Source Code.

See the module-specific device tree descriptions and additional/intermediate device on the Device Tree for NXP Based Modules.

Typically, a device tree is defined at multiple levels and composed of multiple device tree files. Device tree files (dts and dtsi) may include other device tree files known as includable device tree files (dtsi). In this manner, a board-level device tree file (dts) generally includes a SoC level device tree file (dtsi). To support the modular approach of Toradex products, our device tree files usually have three levels of inclusion: carrier board, module and SoC level. This is also reflected in the device tree file names, which are composed by the three levels: ${soc}-${module}-${board}.dtb

We provide a carrier board level device tree file (ie. eval-v3) that is compatible with our evaluation carrier boards. Due to the standardized hardware interfaces of the Colibri and Apalis modules, this device tree file often also works for other carrier boards (e.g. our evaluation board device trees do work on the smaller carrier boards like Iris or Ixora). However, a custom device tree may still be required for a custom carrier board to allow enabling non (Colibri/Apalis) standard devices such as secondary Ethernet or disabling unused devices (preventing unnecessary drivers from loading and reducing boot time).

The Linux kernel needs device tree binaries (*.dtb) to boot. These binaries are generated by the device tree compiler from the device tree source files. The compiler is part of the Linux sources and is automatically built if needed. The kernel build system provides the dtbs target which compiles all device trees which are compatible with the current kernel configuration. ARCH and CROSS_COMPILE must be set and the kernel must be configured before device tree binaries can be compiled.

make dtbs

By specifying a single device tree file, a specific device can be built.

make vf500-colibri-eval-v3.dtb

Device Tree Anatomy​

Each supported hardware device has a compatible string. Along with the compatible property, the device-specific properties need to be specified. These properties are specified in the device tree bindings. The most important properties are compatible, reg, clocks, interrupts, and status. A memory-mapped device (UART in this case) looks like this:

Device Tree anatomy

Nodes can be referenced using the ampersand (&) character and the label.

A more detailed description of the device tree data structure can be found at

NXP makes available an Application Note entitled Introduction to Device Trees.

Customizing The Device Tree​

Before starting the customization please have a look at the exact device tree layout of the module you are using (see below). Then, a straight forward way to start is copying the file of the carrier board level device tree, e.g. by executing the following command from within the kernel source tree:

cp arch/arm/boot/dts/vf610-colibri-eval-v3.dts arch/arm/boot/dts/vf610-colibri-my-carrier.dts

As a next step you need to extend the Makefile. Edit arch/arm/boot/dts/Makefile and insert vf610-colibri-my-carrier.dtb right after vf610-colibri-eval-v3.dtb:

dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
vf610-colibri-eval-v3.dtb \
vf610-colibri-my-carrier.dtb \
vf500-colibri-dual-eth.dtb \
vf610-colibri-dual-eth.dtb \
vf610-cosmic.dtb \

The command make dtbs should now compile also this new device tree binary. We recommend altering only this carrier board level device tree using the techniques below.


The kernel build system writes the combined device tree to the drive, e.g. arch/arm/boot/dts/.vf610-colibri-my-carrier.dtb.dts.tmp. The combined dts file can be handy to debug what the actual device tree file will look like. The combined file is ultimately compiled into the device tree binary representation (*.dtb) which is used by the kernel to boot.

Overwriting properties​

To overwrite a property, the node needs to be referenced using the ampersand character and the label. Later device tree entries overwrite earlier entries (the sequence order of entries is what matters, hence the include order matters). Typically the higher layers (e.g. carrier board device tree) overwrite the lower layers (e.g. SoC device tree) since the higher layers include the lower layers at the very beginning.

E.g. for USB controllers which are capable to be device or host (dual-role), one can overwrite the default mode explicitly using the dr_mode property:

&usbdev0 {
dr_mode = "host";

Activating/Deactivating Devices​

An important device attribute is the status property. It allows devices to be activated/deactivated. A lot of devices are specified in the SoC level device trees but are disabled by default. By referencing the base node (using the ampersand character and the label), the device can be enabled by any of the layers overwriting the status property.

&uart4 {
status = "okay";

Overwriting nodes​

Entire nodes can be overwritten by simply redefining them. Like overwriting properties, latter definitions overwrite earlier definitions.

E.g. to overwrite the pin configuration of Vybrids UART2 (UART_B) overwrite the uart2grp node by simply redefining it in your device tree (this pinctrl specification is already defined in vf-colibri.dtsi, but with the CTS/RTS pins).

&iomuxc {
vf610-colibri {
pinctrl_uart2: uart2grp {
fsl,pins = <
VF610_PAD_PTD0__UART2_TX 0x21a2
VF610_PAD_PTD1__UART2_RX 0x21a1

Delete properties or nodes​

It is also possible to delete properties or even nodes using /delete-property/ or /delete-node/. The following example deletes the fsl,uart-has-rtscts property defined in the carrier board level device tree imx6qdl-colibri.dtsi:

&uart1 {

To delete a node, use its name, e.g.



The device tree allows some device types to be rearranged using aliases. This is useful for RTCs, for instance, since the first RTC device is used as the primary time source for the system. The primary time source should be assigned to the rtc0 alias (in this example we assign snvsrtc as the primary RTC, which is Vybrids internal RTC):

    aliases {
rtc0 = &snvsrtc;
rtc1 = &rtc;

Referencing nodes​

If resources of another device are required, a reference is used to connect the two devices. Typically this is used to assign resources such as interrupts, clocks, GPIOs or PWM channels to a device. Depending on the referenced device, a specific amount of parameters (cells) are necessary. The amount is defined in the -cells property of the parent device.


A GPIO specification needs a reference to a GPIO node and one or more cells (arguments). The amount of cells is driver specific. It can be obtained from the device tree binding documentation or by looking at the GPIO controller node (a device which exports GPIO is marked with the gpio-controller property). The #gpio-cells property defines how many cells are expected. E.g. Vybrid's GPIO controller is defined as follows in vfxxx.dtsi:

gpio1: gpio@4004a000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
#gpio-cells = <2>;

This means that the GPIO need to be referenced using two cells, e.g.

    cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;

This example assigns a single GPIO from the GPIO controller with the label gpio1 (referenced using the ampersand character &), and passes it the two cells with a value of 10 and GPIO_ACTIVE_LOW. The meaning/order of the cells depends on the parent device type. The parent device's device tree binding documentation should contain more information on that.

The NXP based modules share a common GPIO cells format (see Documentation/devicetree/bindings/gpio/gpio-mxs.txt and gpio-vf610.txt):

- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low

This explains the meaning of the two cells from the example above:

    cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
  • The first cell (10) is the GPIO number within the referenced GPIO bank.
  • The second cell (GPIO_ACTIVE_LOW) specifies the GPIO polarity (GPIO_ACTIVE_LOW is a preprocessor macro defined as 1).


Also, the interrupt controller specifies the number of cells required. The SoC internal interrupts are already assigned to the peripherals in the SoC level device tree, hence those most often do not need further handling. For external devices often GPIOs are used as an interrupt source. To make GPIO's available as interrupt sources, the GPIO controllers node is also annotated with the interrupt-controller property:

gpio1: gpio@40049000 {
compatible = "fsl,vf610-gpio";
#interrupt-cells = <2>;

Interrupts can be assigned in a similar fashion, however, instead of using the linked parent as part of the interrupt specification, the interrupt-parent property needs to be used:

interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;

This example assigns GPIO 10 of the GPIO bank represented by gpio1 as the interrupt of a device.


Almost all peripherals need signals multiplexed to external pins in order to operate. The Linux kernel introduced the pinctrl subsystem around 3.1/3.2 and has especially become important in the device tree world. The exact workings of pinctrl (muxing, pin configuration etc.) vary quite a bit between different SoC vendors; therefore, device tree bindings are not standardized across our modules. Refer to the module-specific sections below for how to define a pinctrl block for the module you are using.

However, assigning pins to a driver works with standardized bindings. Each pinctrl subnode needs to be assigned to a driver, otherwise, the pinctrl won't apply the settings on its own. How and how many pinctrl groups can be assigned to a device depends on the device driver used. Most drivers are documented in the kernel source under Documentation/devicetree/bindings/ (search using the compatible string). Most drivers do not have specific pinctrl requirements and a default assignment can be made using pinctrl-0 for the pinctrl reference and a property pinctrl-names with the name "default", e.g.:

    pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mydevice>;

To verify that a certain pinctrl has been picked up by the driver and correctly applied, the debug information available via sysfs can be helpful:

# cat /sys/kernel/debug/pinctrl/pinctrl-handles

Device Tree Bindings​

The device tree bindings for most supported hardware devices are documented in the kernel source tree inside the folder Documentation/devicetree/bindings/. One can also read the latest version of them online at However, bindings might have been changed between the actual kernel version used and the one documented online; hence when in doubt, use the documentation in the source tree.

Another source of device tree bindings are those provided by other boards. The device tree folder arch/arm/boot/dts/ contains a vast amount of supported ARM boards which might make use of device tree bindings for already supported hardware.

Device Tree for NXP Based Modules​

i.MX 6 Based Modules​

The modules Colibri iMX6S/iMX6DL share the same device tree binary, so do the modules Apalis iMX6D/iMX6Q. Click on the box to see the current version of the respective device tree file.

Apalis/Colibri iMX6 device tree structure

Pinmux (iMX6)​

Pin configuration such as pinmux or drive strength is either set by pinctrl-imx6dl or the pinctrl-imx6q driver. The SoC level device trees define the base configuration and allow to extend entries through the iomuxc label.

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Cells need to be assigned to the property, each pin requires 5 cells. However, the first four are usually given by a pre-processor macro (see arch/arm/boot/dts/imx6dl-pinfunc.h or imx6q-pinfunc.h respectively). The macros consist of three parts, a prefix, the pad (or ball) name (as used in datasheets) and the alternate function name. Since each pad has multiple alternate functions, there are multiple macros for a single pad, all ending with a different alternate function. It is crucial to select the correct macro for the intended use (e.g. the macro which contains GPIO as an alternate function if the pad is going to be used as a GPIO).


Prefix: MX6QDL_PAD
Pad/ball name: EIM_A24
Alternate function: GPIO5_IO04

The 5th and last cell of a pin muxing entry need to be provided as a number in the device tree. This last cell contains the pin settings typically in a hexadecimal notation. Additionally, the last cell's bit 30 is used to give the setting of the SION bit, bit 31 prevents the iomuxc from changing the pad control register (see here for details).

pinctrl_additionalgpio: additionalgpios {
fsl,pins = <
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0

There are preprocessor define for commonly used default pin configurations (e.g. PAD_CTRL_HYS_PU).

The bitwise definition for the last cell is given by the registers of the i.MX 6 Input/Output Multiplexer Controller.

16HYS0 - CMOS input
1 - Schmitt trigger input
15-14PUS00 - 100 kOhm Pull Down
01 - 47 kOhm Pull Up
10 - 100 kOhm Pull Up
11 - 22 kOhm Pull Up
13PUE0 - Keeper enable
1 - Pull enable
Selection between keeper and pull up/down function
12PKE0 - Pull/Keeper Disabled
1 - Pull/Keeper Enabled Enable
enable keeper or pull up/down function
11ODE0 - Output is CMOS
1 - Output is open drain
7-6SPEED00 - Low (50 MHz)
01 - Medium (100,150 MHz)
10 - Medium (100,150 MHz)
11 - High (100,150,200 MHz)
5-3DSE000 - output driver disabled (Hi Z)
001 - 150 Ohm (240 Ohm if pad is DDR)
010 - 75 Ohm (120 Ohm if pad is DDR)
011 - 50 Ohm (80 Ohm if pad is DDR)
100 - 37 Ohm 60 hm if pad is DDR)
101 - 30 Ohm (48 Ohm if pad is DDR)
110 - 25 Ohm
111 - 20 Ohm (34 Ohm if pad is DDR)
0SRE0 - Slow Slew Rate
1 - Fast Slew Rate

For further details see Chapter 4 of the Toradex Colibri or Apalis iMX6 datasheet or/and Chapter 36 of the NXP®/Freescale i.MX 6 application processor reference manual.

Device Tree Overlays​

Device Tree Overlays (DTOs) provide a way to modify the overall device tree without re-compiling the complete device tree. Overlays are small pieces or fragments of an entire device tree. They can be added or removed as needed, often enabling/disabling hardware components in the system.

Device Tree Overlays were introduced in BSP 5. Therefore this information does not apply to earlier BSPs.

See the Device Tree Overlays article, for specific information.

Device Tree Customization Examples​

The examples are collected in a separate article:

Device Tree Customization Examples

Webinar: Demystifying Device Tree for NXP® i.MX Processors​

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