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Pinmuxing AM6X Based Modules

Introduction​

This article aims to give you a comprehensive understanding of pinmuxing on AM6X based modules. You will be equipped with the knowledge necessary to configure pins effectively, leveraging the specifics on how to change and assign functions to AM6X SoC pins that suits to your hardware design, diving into the intricacies of the IOPAD and discuss how to configure pins effectively using device tree nodes and the pinctrl-single,pins property.

Why Pinmuxing​

Pin configuration is a critical aspect to guarantee that your custom hardware behaves as expected, assigning specific functions to the right pins. Powered by TI's AM6X system-on-chips (SoCs), these modules offer a powerful Input/Output PAD (IOPAD) that enables pin multiplexing and flexible pin configurations, including drive strength.

Prerequisites​

  • Toradex with AM6X based SoC: Verdin AM62

Pinmuxing Details​

To configure a pin on AM6X based modules, a device tree node must be defined inside the pin controller node, with the property pinctrl-single,pins with the specific definitions found in k3-pinctrl.h and the related Technical Reference Manual.

TI AM6x Based Modules​

To configure a pin, a device tree node is required inside the pin controller node with the property pinctrl-single,pins. Three values must be assigned to the property for each pin, with the first one been related to the relative address of the PAD, the second one been related to the signal's direction of the PAD, and the third one been related to the number of the alternate function. These #define statements specify the desired function for a given SoC pin. For instance, in the example below, a GPIO pin can be muxed from SPI0_CS0 to EHRPWM0_A.

/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi

&main_pmx0 {
    /* Verdin PWM_1 */
    pinctrl_epwm0_a: main-epwm0a-pins-default {
        pinctrl-single,pins = <
            AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */
        >;
    };

The relative address of the PAD can be found using the physical address of the PAD given by the AM62x Sitara Processors Technical Reference Manual and subtracting the value related to the mux node. For example, the physical address of SPI0_CS0 is 0xF41B4h and was found on the Table 14-6173 of the AM62x Texas Instruments Technical Reference Manual, the value related to the &main_pmx0 node is 0xF4000h and was found on arch/arm64/boot/dts/ti/k3-am62-main.dtsi. The subtraction gives us 0x01b4h, which is our relative address.

For a detailed description and table of possible pin-settings, look them up in the AM62x Texas Instruments Technical Reference Manual. The possible muxings can be found in chapter 4 of the datasheet or with our Pinout Designer pinout.torizon.io.



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