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Pinmuxing i.MX 8/8X Based Modules

Introduction​

This article aims to give you a comprehensive understanding of pinmuxing on i.MX 8/8X based modules. You will be equipped with the knowledge necessary to configure pins effectively, leveraging the specifics on how to change and assign functions to i.MX 8/8X SoC pins that suits to your hardware design, diving into the intricacies of the IOMUXC and discuss how to configure pins effectively using device tree nodes and the fsl,pins property.

Why Pinmuxing​

Pin configuration is a critical aspect to guarantee that your custom hardware behaves as expected, assigning specific functions to the right pins. Powered by NXP's i.MX 8 and i.MX 8X system-on-chips (SoCs), these modules offer extensive pin multiplexing capabilities through their Input/Output Multiplexer Controllers (IOMUXC). The capability to set pin configurations, such as pinmux and drive strength, provides developers with flexibility and control over the module's functionality.

Prerequisites​

  • Toradex with i.MX 8/8X based SoC: Colibri iMX8X or Apalis iMX8

Pinmuxing Details​

The i.MX 8/8X based System on Chips (SoCs) enables the multiplexing of pins through its Input/Output Multiplexer Controller (IOMUXC). The SoC level device trees define the driver node for this controller. All pin muxing and drive strength configurations are managed in the System Controller Unit, which is a dedicated M-Core that runs the System Controller Firmware (SCFW). The Linux IOMUXC driver cannot directly access the IOMUXC registers but communicates with its firmware (SCFW) through the SCU driver.

NXP i.MX 8 Based Modules​

To configure a pin, a device tree node is required inside the pin controller node with the property fsl,pins. Each pin requires three integers to be assigned to the property. The first two integers are typically given by preprocessor definitions found in include/dt-bindings/pinctrl/pads-imx8qm.h.

These #define statements specify the SoC pin and its desired function. The third integer defines the pin settings in hexadecimal notation. In the examples provided, the pin ADC_IN0 is muxed to the function ADC0_IN0, for i.MX 8.

&iomuxc {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, ...
    
    /* Apalis AN1_ADC */
    pinctrl_adc0: adc0grp {
        fsl,pins =
            /* Apalis AN1_ADC0 */
            <IMX8QM_ADC_IN0_DMA_ADC0_IN0                0xc0000060>,
            ...
    };

For further details and a table of possible pin settings, refer to the i.MX 8QuadMax Applications Processor Reference Manual. The possible muxings are listed in chapter 4 of the datasheets or can be found using the Pinout Designer tool available at pinout.torizon.io.

NXP i.MX 8X Based Modules​

To configure a pin, a device tree node is required inside the pin controller node with the property fsl,pins. Each pin requires three integers to be assigned to the property. The first two integers are typically given by preprocessor definitions found in:

  • include/dt-bindings/pinctrl/pads-imx8qxp.h
  • include/dt-bindings/pinctrl/pads-imx8dxl.h

These #define statements specify the SoC pin and its desired function. The third integer defines the pin settings in hexadecimal notation. In the examples provided, the pin FLEXCAN0_TX is muxed to the function ADMA_FLEXCAN0_TX, for i.MX 8X.

&iomuxc {
...
        colibri-imx8qxp {
                pinctrl_flexcan1: flexcan0grp {
                        fsl,pins = <
                                IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX            0x21
                                IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX            0x21
                        >;
                };
        };
...
};

For further details and a table of possible pin settings, refer to Chapter 9.2 - IOMUXD of the i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual. The possible muxings are listed in chapter 4 of the respective module datasheets or can be found using the Pinout Designer tool available at pinout.torizon.io.



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