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Pinmuxing i.MX 6/6ULL Based Modules

Introduction​

This article aims to give you a comprehensive understanding of pinmuxing on i.MX 6/6ULL based modules, exploring the process of pinmuxing while discussing the role of the pinctrl-imx6dl and pinctrl-imx6q drivers, which are responsible for configuring pins on Colibri iMX6S, Colibri iMX6DL, Apalis iMX6Q, and Apalis iMX6D modules, respectively. You will be equipped with the knowledge necessary to configure pins effectively, leveraging the the specifics on how to change and assign functions to i.MX 6/6ULL SoC pins that suits to your hardware design.

Why Pinmuxing​

Pin configuration is a critical aspect to guarantee that your custom hardware behaves as expected, assigning specific functions to the right pins. These modules, powered by NXP's i.MX 6 and i.MX 6ULL system-on-chips (SoCs), offer extensive pin multiplexing capabilities through their Input/Output Multiplexer Controllers (IOMUXC). The capability to set pin configurations, such as pinmux and drive strength, provides developers with flexibility and control over the module's functionality.

Prerequisites​

  • Toradex with NXP i.MX 6 based SoC: Apalis or Colibri iMX6

Pinmuxing Details​

For i.MX 6/6ULL based modules, pin configuration involves assigning a device tree node with the property fsl,pins inside the pin controller node. Each pin requires five cells, with the first four often provided by pre-processor macros. These macros consist of a prefix, the pad (or ball) name, and the alternate function name. Choosing the correct macro is crucial, as it determines the intended use of the pin. The fifth cell, represented as a hexadecimal number in the device tree, contains the pin settings and controls additional features like the SION bit.

NXP i.MX 6 Based Modules​

Pin configuration such as pinmux or drive strength is either set by pinctrl-imx6dl driver, for Colibri iMX6S or Colibri iMX6DL, or the pinctrl-imx6q driver, for Apalis iMX6Q or Apalis iMX6D. The SoC level device trees define the base configuration and allow to extend entries through the iomuxc label.

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Cells need to be assigned to the property, each pin requires 5 cells. However, the first four are usually given by a pre-processor macro (see arch/arm/boot/dts/imx6dl-pinfunc.h or imx6q-pinfunc.h). The macros consist of three parts, a prefix, the pad (or ball) name (as used in datasheets), and the alternate function name. Since each pad has multiple alternate functions, there are multiple macros for a single pad, all ending with a different alternate function. It is crucial to select the correct macro for the intended use (e.g. the macro which contains GPIO as an alternate function if the pad is going to be used as a GPIO).

MX6QDL_PAD_EIM_A24__GPIO5_IO04

Prefix: MX6QDL_PAD
Pad/ball name: EIM_A24
Alternate function: GPIO5_IO04

The 5th and last cell of a pin muxing entry need to be provided as a number in the device tree. This last cell contains the pin settings typically in a hexadecimal notation. Additionally, the last cell's bit 30 is used to give the setting of the SION bit, bit 31 prevents the iomuxc from changing the pad control register.

pinctrl_csi_gpio_2: csigpio2grp {
    fsl,pins = <
        MX6QDL_PAD_EIM_A24__GPIO5_IO04   0x1b0b0
    >;
};

There are preprocessor definitions for commonly used pin configurations (e.g. PAD_CTRL_HYS_PU). The bitwise definition for the last cell is given by the registers of the i.MX 6 Input/Output Multiplexer Controller. For further details see Chapter 4 of the Toradex Colibri iMX6 datasheet or Apalis iMX6 datasheet, the NXP® i.MX 6Solo/6DualLite Applications Processor Reference Manual and/or NXP® i.MX 6Dual/6Quad Applications Processor Reference Manual.

NXP i.MX 6ULL Based Modules​

The i.MX 6ULL SoC allows multiplexing pins through its Input/Output Multiplexer Controller (IOMUXC). Besides multiplexing pins, this controller also allows setting pin configurations such as drive strength. There are two largely independent controllers: the IOMUXC and the IOMUXC LPSR (low-power pin controller). The SoC level device trees define the driver node for each of these controllers which bind to the pinctrl-imx6ul driver and defines the labels iomuxc and iomuxc_lpsr to give lower-level device tree access to the node.

To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Cells need to be assigned to the property, each pin requires 5 cells. However, the first four are usually given by a pre-processor macro (see arch/arm/boot/dts/imx6ull-pinfunc.h or arch/arm/boot/dts/imx6ull-pinfunc-lpsr.h), only the last cell needs to be provided. This last cell contains the pin settings in a hexadecimal notation. Additionally, the last cell's bit 30 is used to give the setting of the SION bit, bit 31 prevents the iomuxc from changing the pad control register. Since i.MX 6ULL SoC shares pin assignments with the i.MX 6UL SoC, various pin assignments for both processors are in the file arch/arm/boot/dts/imx6ul-pinfunc.h, which is included in arch/arm/boot/dts/imx6ull-pinfunc.h.

&iomuxc {
...
    pinctrl_can_int: canintgrp {
        fsl,pins = <
            MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04    0x13010 /* SODIMM 73 */
        >;
    };
...
};

The bitwise definition for the last cell is given by the PAD Control Registers of the i.MX 6ULL Input/Output Multiplexer Controller. For further details see Chapter 4 of the Colibri iMX6ULL datasheet or/and the NXP®/Freescale i.MX 6ULL application processor reference manual.



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