Pinmuxing i.MX 7 Based Modules
Introduction
This article aims to give you a comprehensive understanding of pinmuxing on i.MX 7 based modules. You will be equipped with the knowledge necessary to configure pins effectively, leveraging the the specifics on how to change and assign functions to i.MX7 SoC pins that suits to your hardware design.
Why Pinmuxing
Pin configuration is a critical aspect to guarantee that your custom hardware behaves as expected, assigning specific functions to the right pins. These modules, powered by NXP's i.MX 7 system-on-chip (SoC), offer extensive pin multiplexing capabilities through their Input/Output Multiplexer Controllers (IOMUXC). The capability to set pin configurations, such as pinmux and drive strength, provides developers with flexibility and control over the module's functionality.
Prerequisites
- Toradex with NXP i.MX 7 based SoC: Colibri iMX7
Pinmuxing Details
The i.MX 7 SoC allows multiplexing pins through its Input/Output Multiplexer Controller (IOMUXC). Besides multiplexing pins, this controller also allows setting pin configurations such as drive strength. There are two largely independent controllers: the IOMUXC and the IOMUXC LPSR (low-power pin controller). The SoC level device trees define the driver node for each of these controllers which bind to the pinctrl-imx7 driver and defines the labels iomuxc and iomuxc_lpsr to give lower-level device tree access to the node.
NXP i.MX 7 Based Modules
To configure a pin, a device tree node inside the pin controller node with the property fsl,pins is required. Cells need to be assigned to the property, each pin requires 5 cells. However, the first four are usually given by a pre-processor macro (see arch/arm/boot/dts/imx7d-pinfunc.h or arch/arm/boot/dts/imx7d-pinfunc-lpsr.h), only the last cell needs to be provided. This last cell contains the pin settings in a hexadecimal notation. Additionally, the last cell's bit 30 is used to give the setting of the SION bit, bit 31 prevents the iomuxc from changing the pad control register.
&iomuxc {
...
pinctrl_can_int: canintgrp {
fsl,pins = <
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x14 /* SODIMM 73 */
>;
};
...
};
The bitwise definition for the last cell is given by the PAD Control Registers of the i.MX 7 Input/Output Multiplexer Controller. For further details see Chapter 4 of the Colibri iMX7 datasheet or/and the NXP®/Freescale i.MX 7 application processor reference manuals: i.MX 7Dual Applications Processor Reference Manual and i.MX 7Solo Applications Processor Reference Manual.